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1 of 30 august 31, 2004 ? 2004 integrated device technology, inc. dsc 5701 idt and the idt logo are trademarks of integrated device technology, inc. features rc32300 32-bit microprocessor ? up to 150 mhz operation ? enhanced mips-ii instruction set architecture (isa) ? cache prefetch instruction ? conditional move instruction ? dsp instructions ? supports big or little endian operation ? mmu with 32 page tlb ? 8kb instruction cache, 2-way set associative ? 2kb data cache, 2-way set associative ? cache locking per line ? programmable on a page basis to implement a write-through no write allocate, write-through write allocate, or write-back algorithms for cache management ? compatible with a wide variety of operating systems local bus interface ? up to 75 mhz operation ? 26-bit address bus ? 32-bit data bus ? direct control of local memory and peripherals ? programmable system watch-dog timers ? big or little endian support interrupt controller simplifies exception management four general purpose 32-bit timer/counters programmable i/o (pio) ? input/output/interrupt source ? individually programmable sdram controller (32-bit memory only) ? 4 banks, non-interleaved ? up to 512mb total sdram memory supported ? implements full, direct control of discrete, sodimm, or dimm memories ? supports 16mb through 512mb sdram device depths ? automatic refresh generation serial peripheral interface (spi) master mode interface uart interface ? two 16550 compatible uarts ? baud rate support up to 1.5 mb/s ? modem control signals available on one channel memory & peripheral controller ? 6 banks, up to 64mb per bank ? supports 8-,16-, and 32-bit interfaces ? supports flash rom, sram, dual-port memory, and peripheral devices ? supports external wait-state generation ? 8-bit boot prom support ? flexible i/o timing protocols block diagram figure 1 rc32334 block diagram note: this data sheet does not apply to revision z silicon. contact your idt sales representative for information on revision z. local memory/io control interrupt contro l dma control dual uart 32-bit timers spi control programmable i/o pci bridge idt peripheral bus riscore32300 enhanced mips-ii isa integer cpu rc5000 compatible cp0 32-page tlb ejtag in-circuit emulator interface 2kb 2-set, lockable data cache 8kb 2-set lockable instr. cache ipbus bridge sdram control 79rc32334?rev. y idt tm interprise tm integrated communications processor
2 of 30 august 31, 2004 idt 79rc32334?rev. y 4 dma channels ? 4 general purpose dma, each with endianess swappers and byte lane data alignment ? supports scatter/gather, chaining via linked lists of records ? supports memory-to-memory, memory-to-i/o, memory-to- pci, pci-to-pci, and i/o-to-i/o transfers ? supports unaligned transfers ? supports burst transfers ? programmable dma bus transactions burst size (up to 16 bytes) pci bus interface ? 32-bit pci, up to 66 mhz ? revision 2.2 compatible ? target or master ? host or satellite ? three slot pci arbiter ? serial eeprom support, for loading configuration registers off-the-shelf development tools jtag interface (ieee std. 1149.1 compatible) 256-ball bga (1.0mm spacing) 3.3v operation with 5v tolerant i/o ejtag in-circuit emulator interface device overview the idt rc32334 device is an integrated processor based on the rc32300 cpu core. this product incorporates a high-performance, low- cost 32-bit cpu core with functionality common to a large number of embedded applications. the rc32334 integrates these functions to enable the use of low-cost pc commodity market memory and i/o devices, allowing the aggressive price/performance characteristics of the cpu to be realized quickly into low-cost systems. cpu execution core the rc32334 integrates the riscore32300, the same cpu core found in the award-winning rc32364 microprocessor. the riscore32300 implements the enhanced mips-ii isa. thus, it is upwardly compatible with applications written for a wide variety of mips architecture processors, and it is kernel compatible with the modern operating systems that support idt?s 64-bit riscontroller product family. the riscore32300 was explicitly defined and designed for inte- grated processor products such as the rc32334. key attributes of the execution core found within this product include: high-speed, 5-stage scalar pipeline executes to 150mhz. this high performance enables the rc32334 to perform a variety of performance intensive tasks, such as routing, dsp algorithms, etc. 32-bit architecture with enhancements of key capabilities. thus, the rc32334 can execute existing 32-bit programs, while enabling designers to take advantage of recent advances in cpu architecture. count leading-zeroes/ones. these instructions are common to a wide variety of tasks, including modem emulation, voice over ip compression and decompression, etc. cache prefetch instruction support, including a specialized form intended to help memory coherency. system programmers can allocate and stage the use of memory bandwidth to achieve maximum performance. 8kb of 2-way set associative instruction cache figure 2 rc32334 based system diagram sdram flash local i/o serial eeprom serial channels programmable i/o rc32334 integrated core controller 32-bit, 66mhz pci local memory i/o bus
3 of 30 august 31, 2004 idt 79rc32334?rev. y 2kb of 2-way set associative data cache, capable of write-back and write-through operation. cache locking per line to speed real-time systems and critical system functions on-chip tlb to enable multi-tasking in modern operating systems ejtag interface to enable sophisticated low-cost in-circuit emulation. synchronous-dram interface the rc32334 integrates a sdram controller which provides direct control of system syncdram running at speeds to 75mhz. key capabilities of the sdram controller include: direct control of 4 banks of sdram (up to 2 64-bit wide dimms) on-chip page comparators optimize access latency. speeds to 75mhz programmable address map. supports 16, 64, 128, 256, or 512mb sdram devices automatic refresh generation driven by on-chip timer support for discrete devices, sodimm, or dimm modules. thus, systems can take advantage of the full range of commodity memory that is available, enabling system optimization for cost, real- estate, or other attributes. local memory and i/o controller the local memory and i/o controller implements direct control of external memory devices, including the boot rom as well as other memory areas, and also implements di rect control of external periph- erals. the local memory controller is highly flexible, allowing a wide range of devices to be directly controlled by the rc32334 processor. for example, a system can be built using an 8-bit boot rom, 16-bit flash cards (possibly on pcmcia), a 32-bit sram or dual-port memory, and a variety of low-cost peripherals. key capabilities include: direct control of eprom, flash, ram, and dual-port memories 6 chip-select outputs, supporting up to 64mb per memory space supports mixture of 8-, 16-, and 32-bit wide memory regions flexible timing protocols allow direct control of a wide variety of devices programmable address map for 2 chip selects automatic wait state generation. pci bus bridge in order to leverage the wide availability of low-cost peripherals for the pc market as well as to simplify the design of add-in functions, the rc32334 integrates a full 32-bit pci bus bridge. key attributes of this bridge include: 66 mhz operation pci revision 2.2 compliant programmable address mappings between cpu/local memory and pci memory and i/o on-chip pci arbiter extensive buffering allows pci to operate concurrently with local memory transfers selectable byte-ordering swapper 5v tolerant i/o. on-chip dma controller to minimize cpu exception handli ng and maximize the efficiency of system bandwidth, the rc32334 integrates a very sophisticated 4- channel dma controller on chip. the rc32334 dma controller is capable of: chaining and scatter/gather support through the use of a flexible, linked list of dma transaction descriptors capable of memory<->memory, memory<->i/o, and pci<->memory dma unaligned transfer support byte, halfword, word, quadword dma support. on-chip peripherals the rc32334 also integrates peripherals that are common to a wide variety of embedded systems. dual channel 16550 compatible uarts, with modem control interface on one channel. spi master mode interface for direct interface to eeprom, a/d, etc. interrupt controller to speed interrupt decode and management four 32-bit on-chip timer/counters programmable i/o module debug support to facilitate rapid time to market, the rc32334 provides extensive support for system debug. first and foremost, this product integrates an ejtag in-circuit emula- tion module, allowing a low-cost emulator to interoperate with programs executing on the controller. by using an augmented jtag interface, the rc32334 is able to reuse the same low-cost emulators developed around the rc32364 cpu. secondly, the rc32334 implements additional reporting signals intended to simplify the task of system debugging when using a logic analyzer. this product allows the logic analyzer to differentiate transac- tions initiated by dma from those initiated by the cpu and further allows cpu transactions to be sorted into instruction fetches vs. data fetches. finally, the rc32334 implements a full boundary scan capability, allowing board manufacturing diagnostics and debug.
4 of 30 august 31, 2004 idt 79rc32334?rev. y packaging the rc32334 is packaged using a 256-lead pbga package, with 1.0mm ball spacing. thermal considerations the rc32334 consumes less than 2.1 w peak power. the device is guaranteed in an ambient temperature range of 0 to +70 c for commercial temperature devices; -40 to +85 for industrial temperature devices. revision history may 16, 2000: initial version. june 8, 2000 : in cpu core specific signals section of table 1, changed cpu_dr_r_n pin from input to output. updated document from advance to preliminary information. june 15, 2000 : in table 1, switched assertion and de-assertion for debug_cpu_dma_n signal. in the ac timing characteristics table, added spi section and adjusted parameters in the reset section. july 12, 2000 : removed ?preliminary information? statement. added information regarding external pull-ups and pull-downs to the pin description table. made minor revisions in other parts of the data sheet. august 3, 2000 : added pin layout diagram showing power and ground pins. revised power curves section to reflect support of only 2x, 3x, and 4x. august 30, 2000 : added standby mode and values to power consumption table. extended power curve figure to 75 mhz. september 25, 2000 : changed mips32 isa to enhanced mips-ii. in local system interface section of table 6, changed thld2 values for mem_data[31:0] from 1.8 to 1.5 ns and changed tdoh3 values for mem_addr[25:2], etc. from 1.8 to 1.5 ns. december 12, 2000 : changed max values for cpu_masterclock period in table 5 and added footnote. in table 1, added 2nd alternate function for spi_mosi, spi_miso, spi_sck. in table 10, removed the ?1? from alt column for cpu_masterclk and added ?2? in alt column for pins g3, g4, h2. in rc32334 alternate signal functions table: added pin t2; added pin names in alt #2 column for pins g3, g4, h2; added pio[11] to alt #2 column for pin r3. january 4, 2001 : in table 6 under interrupt handling, moved the values for tsu9 from the max to the min columns. march 13, 2001 : changed upper ambient temperature for industrial and commercial uses from +70 c to +85 c. june 7, 2001 : in the clock parameters table, added footnote 3 to output_clk category and added na to min and max columns. in figure 3 (reset specification), enhanced signal line for cpu_masterclk. in local system interface section of ac timing characteristics table, changed values in min column for last category of signals (tdoh3) from 1.5 to 2.5 for all speeds. in sdram controller section of same table, changed values in min column for last category of signals (9 signals) from 1 to 2.5 for all speeds. september 14, 2001 : in the reset category of table 6: switched mem_addr[19:17] from tsu22 and thld22 to tsu10 and thld10; switched mem_addr[22:20] from tsu10 and thld10 to tsu22 and thld22; moved ejtag_pcst[2:0] from reset to debug interface category under tsu20 and thld20. november 1, 2001 : added input voltage undershoot parameter and 2 footnotes to table 10. march 20, 2002 : in local system interface section of ac timing characteristics table, changed values in min column for last category of signals (tdoh3) from 2.5 to 1.5 for all speeds. in table 8, pci drive output pads, the conditions for parameters v ol , v oh , v il , and v ih were changed to read per pci 2.2. may 2, 2002 : changed upper ambient temperature for commercial uses back from +85 c to +70 c (changed erroneously from 70 to 85 on march 13, 2001). added reset state status column to table 1. revised description of jtag_trst_n in table 1 and changed this pin to a pull-down instead of a pull-up. july 3, 2002 : this data sheet now describes revision y silicon and is no longer applicable to revision z. july 12, 2002 : in table 6: pci section, changed thld min values from 1 to zero; dma section, changed thld9 min values from 2 to 1; in pio section, changed thld9 min values from 2 to 1; in timer section, changed thld10 min values from 2 to 1. revision y data sheet changed from preliminary to final. september 18, 2002 : added cpu_coldreset_n rise time to table 5, clock parameters. added mem_addr[16] and sdram_addr[16] to tables 1 and 12. changed logic diagram to include sdram_addr[16]. december 18, 2002 : in the reset section of table 6, ac timing characteristics, setup and hold time categories for cpu_coldreset_n have been deleted. july 30, 2003 : in table 8, added 3 new categories (input pads, pci input pads, and all pads) and added footnotes 2 and 3. march 24, 2004 : in table 1, changed description in satellite mode for pci_rst_n. specified ?cold? reset on pages 11 and 12. changed the maximum value for vcc to 4.0 in table 10, absolute maximum ratings, and changed footnote 1 to that table. added power ramp-up section on page 21. august 31, 2004 : added ?green? orderable parts on page 30.
5 of 30 august 31, 2004 idt 79rc32334?rev. y pin description table the following table lists the pins provided on the rc32334. note t hat those pin names followed by ?_n? are active-low signals. all external pull-ups and pull-downs require 10 k ? resistor. name type reset state status drive strength capability description local system interface mem_data[31:0] i/o z high local system data bus primary data bus for memory. i/o and sdram. mem_addr[25:2] i/o [25:10] z [9:2] l [25:17] low [16:2] high memory address bus these signals provide the memory or dram address, during a memory or dram bus transaction. during each word data, the address increments either in linear or sub-block ordering, depending on the transac- tion type. the table below indicates how the memory write enable signals are used to address discreet memory port width types. mem_addr[22] alternate function: reset_boot_mode[1]. mem_addr[21] alternate function: reset_boot_mode[0]. mem_addr[20] alternate function: reset_pci_host_mode. mem_addr[19] alternate function: modebit [9]. mem_addr[18] alternate function: modebit [8]. mem_addr[17] alternate function: modebit [7]. mem_addr[16] alternate function: sdram_addr[16]. mem_addr[15] alternate function: sdram_addr[15]. mem_addr[14] alternate function: sdram_addr[14]. mem_addr[13] alternate function: sdram_addr[13]. mem_addr[11] alternate function: sdram_addr[11]. mem_addr[10] alternate function: sdram_addr[10]. mem_addr[9] alternate function: sdram_addr[9]. mem_addr[8] alternate function: sdram_addr[8]. mem_addr[7] alternate function: sdram_addr[7]. mem_addr[6] alternate function: sdram_addr[6]. mem_addr[5] alternate function: sdram_addr[5]. mem_addr[4] alternate function: sdram_addr[4]. mem_addr[3] alternate function: sdram_addr[3]. mem_addr[2] alternate function: sdram_addr[2]. mem_cs_n[5:0] output h low with internal pull-up memory chip select negated recommend external pull-up. signals that a memory bank is actively selected. mem_oe_n output h high memory output enable negated recommend external pull-up. signals that a memory bank can output its data lines onto the cpu_ad bus. table 1 pin description (part 1 of 7) port width pin signals mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] dma (32-bit) mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 16-bit byte high write enable mem_addr[1] not used (driven low) byte low write enable 8-bit not used (driven high) mem_addr[1] mem_addr[0] byte write enable
6 of 30 august 31, 2004 idt 79rc32334?rev. y mem_we_n[3:0] output h high memory write enable negated bus signals which bytes are to be written during a memory transaction. bits act as byte enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing. mem_wait_n input ? memory wait negated requires external pull-up. sram/ioi/iom modes: allows external wait-states to be injected during last cycle before data is sampled. dpm (dual-port) mode: allows dual-port busy signal to restart memory transaction. alternate function: sdram_wait_n. mem_245_oe_n output h low memory fct245 output enable negated controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to a memory or i/o bank. mem_245_dt_r_n output z high memory fct245 direction xmit/rcv negated recommend external pull-up. alternate function: cpu_dt_r_n. see cpu core specific signals below. output_clk output cpu_mas terclk high output clock optional clock output. pci interface pci_ad[31:0] i/o z pci pci multiplexed address/data bus address driven by bus master during initial frame_n assertion, and then the data is driven by the bus master during writes; or the data is driven by the bus slave during reads. pci_cbe_n[3:0] i/o z pci pci multiplexed command/byte enable bus command (not negated) bus driven by the bus master during the initial frame_n assertion. byte enable negated bus driven by the bus master during the data phase(s). pci_par i/o z pci pci parity even parity of the pci_ad[31:0] bus. driven by bus master during address and write data phases. driven by the bus slave during the read data phase. pci_frame_n i/o z pci pci frame negated driven by the bus master. assertion indicates the beginning of a bus transaction. de-assertion indicates the last datum. pci_trdy_n i/o z pci pci target ready negated driven by the bus slave to indicate the current datum can complete. pci_irdy_n i/o z pci pci initiator ready negated driven by the bus master to indicate that the current datum can complete. pci_stop_n i/o z pci pci stop negated driven by the bus slave to terminate the current bus transaction. pci_idsel_n input ? pci initialization device select uses pci_req_n[2] pin. see the pci subsection. pci_perr_n i/o z pci pci parity error negated driven by the receiving bus agent 2 clocks after the data is received, if a parity error occurs. pci_serr_n i/o open- collector zpci system error external pull-up resistor is required. driven by any agent to indicate an address parity error, data parity during a special cycle command, or any other system error. pci_clk input ? pci clock clock for pci bus transactions. uses the rising edge for all timing references. name type reset state status drive strength capability description table 1 pin description (part 2 of 7)
7 of 30 august 31, 2004 idt 79rc32334?rev. y pci_rst_n input l ? pci reset negated host mode: resets all pci related logic. satellite mode: resets all pci related logic and also warm resets the 32334. pci_devsel_n i/o z pci pci device select negated driven by the target to indicate that the target has decoded the present address as a target address. pci_req_n[2] input z ? pci bus request #2 negated requires external pull-up. host mode: pci_req_n[2] is an input indicating a request from an external device. satellite mode: used as pci_idsel pin which selects this device during a configuration read or write. alternate function: pci_idsel (satellite). pci_req_n[1] input z ? pci bus request #1 negated requires external pull-up. host mode: pci_req_n[1] is an input indicating a request from an external device. alternate function: unused (satellite). pci_req_n[0] i/o z high pci bus request #0 negated requires external pull-up for burst mode. host mode: pci_req_n[0] is an input indicating a request from an external device. satellite mode: pci_req_n[0] is an output indicating a request from this device. pci_gnt_n[2] output z 1 high pci bus grant #2 negated recommend external pull-up. host mode: pci_gnt_n[2] is an output indicating a grant to an external device. satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin. alternate function: pci_inta_n (satellite). pci_gnt_n[1] / pci_eeprom_cs i/o x for 1 pci clock then h 2 high pci bus grant #1 negated recommend external pull-up. host mode: pci_gnt_n[1] is an output indicating a grant to an external device. satellite mode: used as pci_eprom_cs output pin for serial chip select for loading pci configuration registers in the rc32334 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pci_eeprom_cs (satellite). 2nd alternate function: pio[11]. pci_gnt_n[0] i/o z high pci bus grant #0 negated host mode: pci_gnt_n[0] is an output indicating a grant to an external device. recommend external pull- up. satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. require external pull-up. pci_inta_n output open- collector zpci pci interrupt #a negated uses pci_gnt_n[2]. see the pci subsection. pci_lock_n input ? pci lock negated driven by the bus master to indicate that an exclusive operation is occurring. 1 z in host mode; l in satellite non-boot mode; z in satellite boot mode. 2 h in host mode; l in satellite non-boot and boot modes. x = unknown. sdram control interface sdram_addr_12 output l high sdram address bit 12 and precharge all sdram mode: provides sdram address bit 12 (10 on the sdram chip) during row address and "pre- charge all" signal during refresh, read and write command. sdram_ras_n output h high sdram ras negated sdram mode: provides sdram ras control signal to all sdram banks. name type reset state status drive strength capability description table 1 pin description (part 3 of 7)
8 of 30 august 31, 2004 idt 79rc32334?rev. y sdram_cas_n output h high sdram cas negated sdram mode: provides sdram cas control signal to all sdram banks. sdram_we_n output h high sdram we negated sdram mode: provides sdram we control signal to all sdram banks. sdram_cke output h high sdram clock enable sdram mode: provides clock enable to all sdram banks. sdram_cs_n[3:0] output h high sdram chip select negated bus recommend external pull-up. sdram mode: provides chip select to each sdram bank. sodimm mode: provides upper select byte enables [7:4]. sdram_s_n[1:0] output h high sdram sodimm select negated bus sdram mode: not used. sdram sodimm mode: upper and lower chip selects. sdram_bemask_n [3:0] output h high sdram byte enable mask negated bus (dqm) sdram mode: provides byte enables for each byte lane of all dram banks. sodimm mode: provides lower select byte enables [3:0]. sdram_245_oe_n output h low sdram fct245 output enable negated recommend external pull-up. sdram mode: controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to any dram bank. sdram_245_dt_r_n output z high sdram fct245 direction transmit/receive recommend external pull-up. uses cpu_dt_r_n. see cpu core specific signals below. on-chip peripherals dma_ready_n[1:0] / dma_done_n[1:0] i/o z low dma ready negated bus requires external pull-up. ready mode: input pin for each general purpose dma channel that can initiate the next datum in the cur- rent dma descriptor frame. done mode: input pin for each general purpose dma channel that can terminate the current dma descrip- tor frame. dma_ready_n[0] 1st alternate function pio[1]; 2nd alternate function: dma_done_n[0]. dma_ready_n[1] 1st alternate function pio[0]; 2nd alternate function: dma_done_n[1]. pio[15:0] i/o see related pins low programmable input/output general purpose pins that can each be configured as a general purpose input or general purpose output. these pins are multiplexed with other pin functions: uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0], pci_gnt_n[1], spi_mosi, spi_miso, spi_sck, spi_ss_n, uart_rx[0], uart_tx[0], uart_rx[1], uart_tx[1], timer_tc_n[0], dma_ready_n[0], dma_ready_n[1]. note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time. the others default to inputs. timer_tc_n[0] / timer_gate_n[0] i/o z low timer terminal count overflow negated terminal count mode (timer_tc_n): output indicating that the timer has reached its count compare value and has overflowed back to 0. gate mode (timer_gate_n): input indicating that the timer may count one tick on the next clock edge. 1st alternate function: pio[2]. 2nd alternate function: timer_gate_n[0]. uart_rx[1:0] i/o z low uart receive data bus uart mode: each uart channel receives data on their respective input pin. uart_rx[0] alternate function: pio[6]. uart_rx[1] alternate function: pio[4]. name type reset state status drive strength capability description table 1 pin description (part 4 of 7)
9 of 30 august 31, 2004 idt 79rc32334?rev. y uart_tx[1:0] i/o z low uart transmit data bus uart mode: each uart channel sends data on their respective output pin. note that these pins default to inputs at reset time and must be programmed via the pio interface before being used as uart out- puts. uart_tx[0] alternate function: pio[5]. uart_tx[1] alternate function: pio[3]. uart_cts_n[0] uart_dsr_n[0] uart_dtr_n[0] uart_rts_n[0] i/o z low uart transmit data bus uart mode: data bus modem control signal pins for uart channel 0. uart_cts_n[0] alternate function: pio[15]. uart_dsr_n[0] alternate function: pio[14]. uart_dtr_n[0] alternate function: pio[13]. uart_rts_n[0] alternate function: pio[12]. spi_mosi i/o l low spi data output serial mode: output pin from rc32334 as an input to a serial chip for the serial data input stream. in pci satellite mode, acts as an output pin from rc32334 that connects as an input to a serial chip for the serial data input stream for loading pci configuration registers in the rc32334 reset initialization vector pci boot mode. 1st alternate function: pio[10]. defaults to the output direction at reset time. 2nd alternate function: pci_eeprom_mdo. spi_miso i/o z low spi data input serial mode: input pin to rc32334 from the output of a serial chip for the serial data output stream. in pci satellite mode, acts as an input pin from rc32334 that connects as an output to a serial chip for the serial data output stream for loading pci configuration registers in the rc32334 reset initialization vector pci boot mode. defaults to input direction at reset time. 1st alternate function: pio[7]. 2nd alternate function: pci_eeprom_mdi. spi_sck i/o l low spi clock serial mode: output pin for serial clock. in pci satellite mode, acts as an output pin for serial clock for loading pci configuration registers in the rc323334 reset initialization vector pci boot mode. 1st alternate function: pio[9]. defaults to the output direction at reset time. 2nd alternate function: pci_eeprom_sk. spi_ss_n i/o h low spi chip select output pin selecting the serial protocol device as opposed to the pci satellite mode eeprom device. alternate function: pio[8]. defaults to the output direction at reset time. cpu core specific signals cpu_nmi_n input ? cpu non-maskable interrupt requires external pull-up. this interrupt input is active low to the cpu. cpu_masterclk input ? cpu master system clock provides the basic system clock. cpu_int_n[5:4], [2:0] input ? cpu interrupt requires external pull-up. these interrupt inputs are active low to the cpu. cpu_coldreset_n input l ? cpu cold reset this active-low signal is asserted to the rc32334 after v cc becomes valid on the initial power-up. the reset initialization vectors for the rc32334 are latched by cold reset. name type reset state status drive strength capability description table 1 pin description (part 5 of 7)
10 of 30 august 31, 2004 idt 79rc32334?rev. y cpu_dt_r_n output z ? cpu direction transmit/receive this active-low signal controls the dt/r pin of an optional fct245 transceiver bank. it is asserted during read operations. 1st alternate function: mem_245_dt_r_n. 2nd alternate function: sdram_245_dt_r_n. jtag interface signals jtag_tck input ? jtag test clock requires external pull-down. an input test clock used to shift into or out of the boundary-scan register cells. jtag_tck is independent of the system and the processor clock with nominal 50% duty cycle. jtag_tdi, ejtag_dint_n input ? jtag test data in requires an external pull-up on the board. on the rising edge of jtag_tck, serial input data are shifted into either the instruction or data register, depending on the tap controller state. during real mode, this input is used as an interrupt line to stop the debug unit from real time mode and return the debug unit back to run time mode (standard jtag). this pin is also used as the ejtag_dint_n signal in the ejtag mode. jtag_tdo, ejtag_tpc output z high jtag test data out the jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. when no data is shifted out, the jtag_tdo is tri-stated. during real time mode, this signal provides a non- sequential program counter at the processor clock or at a division of processor clock. this pin is also used as the ejtag_tpc signal in the ejtag mode. jtag_tms input ? jtag test mode select requires external pull-up. the logic signal received at the jtag_tms input is decoded by the tap controller to control test operation. jtag_tms is sampled on the rising edge of the jtag_tck. jtag_trst_n input l ? jtag test reset when neither jtag nor ejtag are being used, jtag_trst_n must be driven low (pulled down) or the jtag_tms/ejtag_tms signals must be pulled up and jtag_clk actively clocked. ejtag_dclk output z ? ejtag test clock processor clock. during real time mode, this signal is used to capture address and data from the ejtag_tpc signal at the processor clock speed or any division of the internal pipeline. ejtag_pcst[2:0] i/o z low ejtag pc trace status information 111 (stl) pipe line stall 110 (jmp) branch/jump forms with pc output 101 (brt) branch/jump forms with no pc output 100 (exp) exception generated with an exception vector code output 011 (seq) sequential performance 010 (tst) trace is outputted at pipeline stall time 001 (tsq) trace trigger output at performance time 000 (dbm) run debug mode alternate function: modebit[2:0]. ejtag_debugboot input ? requires external pull- down ejtag debugboot the ejtag_debugboot input is used during reset and forces the cpu core to take a debug exception at the end of the reset sequence instead of a reset exception. this enables the cpu to boot from the ice probe without having the external memory working. this input signal is level sensitive and is not latched inter- nally. this signal will also set the jtagbrk bit in the jtag_control_register[12]. ejtag_tms input ? requires external pull- up ejtag test mode select an external pull-up on the board is required. the ejtag_tms is sampled on the rising edge of jtag_tck. name type reset state status drive strength capability description table 1 pin description (part 6 of 7)
11 of 30 august 31, 2004 idt 79rc32334?rev. y mode bit settings to configure controller on reset the following table lists the mode bit settings to configure the controller on cold reset. debug signals debug_cpu_dma_n i/o z low debug cpu versus dma negated de-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transac- tion was generated from the cpu. assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from dma. alternate function: modebit[6]. debug_cpu_ack_n i/o z low debug cpu acknowledge negated indicates either a data acknowledge to the cpu or dma. alternate function: modebit[4]. debug_cpu_ads_n i/o z low debug cpu address/data strobe negated assertion indicates that either a cpu or a dma transaction is beginning and that the mem_data[31:4] bus has the current block address. alternate function: modebit[5]. debug_cpu_i_d_n i/o z low debug cpu instruction versus data negated assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu or dma data transaction. de-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu instruction transaction. alternate function: modebit[3]. pin mode bit description value mode setting ejtag_pcst[2:0] 2:0 msb (2) clock multiplier masterclock is multiplied internally to gener- ate pclock 0 multiply by 2 1 multiply by 3 2 multiply by 4 3 reserved 4 reserved 5 reserved 6 reserved 7 reserved debug_cpu_i_d_n 3 endbit 0 little-endian ordering 1 big-endian ordering debug_cpu_ack_n 4 reserved 0 debug_cpu_ads_n 5 reserved 0 debug_cpu_dma_n 6 tmrinten enables/disables the timer interrupt on int*[5] 0 enables timer interrupt 1 disables timer interrupt mem_addr[17] 7 reserved for future use 1 table 2 boot-mode configuration settings (part 1 of 2) name type reset state status drive strength capability description table 1 pin description (part 7 of 7)
12 of 30 august 31, 2004 idt 79rc32334?rev. y reset_boot_mode settings by using the non-boot mode cold reset initialization mode the user can change the internal register addresses from base 1800_00 00 to base 1900_0000, as required. the rc32334 cold reset-boot mode initialization setting values and mode descriptions are listed below. pci_host_mode settings during cold reset initialization, the rc32334?s pci interface can be set to the satellite or host mode settings. when set to th e host mode, the cpu must configure the rc32334?s pci configuration registers, includi ng the read-only registers. if the rc32334?s pci is in the pci -boot mode satellite mode, read-only configuration register s are loaded by the serial eeprom. mem_addr[19:18] 9:8 msb (9) boot-prom width specifies the memory port width of the memory space which contains the boot prom. 00 8 bits 01 16 bits 10 32 bits 11 reserved pin reset boot mode description value mode settings mem_addr[22:21] 1:0 msb (1) tri-state memory bus and eeprom bus during cold reset_n assertion 11 tri-state_bus_mode reserved 10 pci-boot mode (pci_host_mode must be in satellite mode) rc32334 will reset either from a cold reset or from a pci reset. boot code is provided via pci. 01 pci_boot_mode standard-boot mode boot from the rc32334?s memory controller (typical system). 00 standard_boot_mode table 3 rc32334 reset_boot_mode initialization settings pin reset boot mode description value mode settings mem_addr[20] pci host mode pci is in satellite mode 1 pci_satellite pci is in host mode (typical system) 0 pci_host table 4 rc32334 pci_host_mode initialization settings pin mode bit description value mode setting table 2 boot-mode configuration settings (part 2 of 2)
13 of 30 august 31, 2004 idt 79rc32334?rev. y logic diagram ? rc32334 rc32334 logic symbol mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] jtag_tck jtag_tms jtag_tdi v cc to i/o gnd mem_wait_n mem_245_oe_n jtag_tdo jtag_trst_n cpu_masterclk cpu_coldreset_n cpu core signals v cc i/o v ss local system jtag power / ground cpu_int_n[5:4],[2:0] cpu_dt_r_n mem_245_dt_r_n spi_mosi spi_miso spi_ss_n spi_sck sdram_addr[12] sdram_ras_n sdram_cas_n sdram_we_n output_clk timer_tc_n[0] uart_rx[1:0] uart_tx[1:0] debug_cpu_ack_n debug pci_ad[31:0] pci_cbe_n[3:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[2:0] pci_gnt_n[2:0] interface pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_cs pci_eeprom_mdo pci_eeprom_sk dma_ready_n[1:0] pio[15:0] pci interface interface mem_addr[25:2] sdram_cke sdram_cs_n[3:0] sdram_bemask_n[3:0] sdram_s_n_[1:0] sdram_245_oe_n dma interface pio timer uart interface v cc to core v cc core sdram_245_dt_r_n mem_data[31:0] cpu_nmi_n debug_cpu_dma_n debug_cpu_ads_n spi interface sdram signals uart_cts_n[0] uart_rts_n[0] uart_dtr_n[0] uart_dsr_n[0] ejtag_tms ejtag_debugboot ejtag_dclk ejtag_pcst[2:0] ejtag debug_cpu_i_d_n sdram_addr[16:13] sdram_addr[11:2] ejtag_tpc v cc p v ss p
14 of 30 august 31, 2004 idt 79rc32334?rev. y clock parameters ? rc32334 (ta = 0 c to +70 c commercial, ta = -40 c to +85 c industrial, v cc i/o = +3.3v 5%,v cc core = +3.3v 5%) reset specification figure 3 mode configuration interface cold reset sequence parameter symbol test conditions rc32334 100mhz rc32334 133mhz rc32334 150mhz units min max min max min max cpu_masterclock high t mchigh transition 2ns 8 ? 6.75 ? 6 ? ns cpu_masterclock low t mclow transition 2ns 8 ? 6.75 ? 6 ? ns cpu_masterclock period 1 1. cpu_masterclock frequency should never be below pci_clk frequency if pci interface is used. t mcp ? 2066.61566.613.3366.6ns cpu_masterclock rise & fall time 2 2. rise and fall times are measured between 10% and 90% t mcrise, t mcfall ??3?3?3ns cpu_masterclock jitter t jitter ??+ 250 ? + 250 ? + 200 ps pci_clk rise & fall time t pcrise, t pcfall pci 2.2 ? 1.6 ? 1.6 ? 1.6 ns pci_clk period 1 t pcp 15 ? 15 ? 15 ? ns jtag_tck rise & fall time t jcrise, t jcfall ??5?5?5ns ejtag_dck period t dck, t 11 10 ? 10 ? 10 ? ns jtag_tck clock period t tck, t 3 100 ? 100 ? 100 ? ns ejtag_dclk high, low time t dck high, t 9 t dck low, t 10 4?4?4?ns ejtag_dclk rise, fall time t dck rise, t 9 t dck fall, t 10 ?1?1?1ns output_clk 3 3. output_clk should not be used in a system. only the cpu_masterclock or its derivative must be used to drive all the subsystems with designs based on the rc32334 device. refer to the rc3233x device errata for more information. tdo21 n/a n/a n/a n/a n/a n/a ? cpu_coldreset_n asserted during power-up power-on sequence 120 ? 120 ? 120 ? ms cpu_coldreset_n rise time t crrise ?5?5?5ns table 5 clock parameters - rc32334 vcc cpu_coldreset_n modebit[9:0] >= 110 ms cpu_masterclk >= 10 ms (mclk) 120 ms t crrise
15 of 30 august 31, 2004 idt 79rc32334?rev. y power ramp-up there is no special requirement for how fast vcc and vccp ramp up to 3.3v. however, all timing references are based on vcc and vccp stabilized at 3.3v -5%. ac timing characteristics ? rc32334 (ta = 0 c to +70 c commercial, ta = -40 c to +85 c industrial, v cc i/o = +3.3v 5%,v cc core = +3.3v 5%) signal symbol reference edge rc32334 1 100mhz rc32334 1 133mhz rc32334 1 150mhz unit user manual timing diagram reference min max min max min max local system interface mem_data[31:0] (data phase) tsu2 cpu_masterclk rising 6 ? 5 ? 4.8 ? ns mem_data[31:0] (data phase) thld2 cpu_masterclk rising 1.5 ? 1.5 ? 1.5 ? ns cpu_dt_r_n tdo3 cpu_masterclk rising ? 15 ? 12 ? 10 ns chapter 9, figures 9.2 and 9.3 mem_data[31:0] tdo4 cpu_masterclk rising ? 12 ? 10 ? 9.3 ns mem_data[31:0] output hold time tdoh1 cpu_masterclk rising 1 ? 1 ? 1 ? ns mem_data[31:0] (tristate disable time) tdz cpu_masterclk rising ? 12 2 ?10 2 ?9.3 2 ns mem_data[31:0] (tristate to data time) tzd cpu_masterclk rising ? 12 2 ?10 2 ?9.3 2 ns mem_wait_n tsu6 cpu_masterclk rising 9 ? 7 ? 6 ? ns mem_wait_n thld8 cpu_masterclk rising 1 ? 1 ? 1 ? ns chapter 10, figures 10.6 through 10.8 mem_addr[25:2] tdo5 cpu_masterclk rising ? 12 ? 9 ? 8 ns mem_cs_n[5:0] tdo6 cpu_masterclk rising ? 12 ? 9 ? 8 ns mem_oe_n, mem_245_oe_n tdo7 cpu_masterclk rising ? 12 ? 9 ? 8 ns mem_we_n[3:0] tdo7a cpu_masterclk rising ? 15 ? 12 ? 10 ns mem_245_dt_r_n tdo8 cpu_masterclk rising ? 15 ? 12 ? 10 ns mem_addr[25:2] mem_cs_n[5:0] mem_oe_n, mem_we_n[3:0], mem_245_dt_r_n, mem_245_oe_n tdoh3 cpu_masterclk rising 1.5 ? 1.5 ? 1.5 ? ns pci pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_lock_n 3 tsu pci_clk rising 3 ? 3 ? 3 ? ns pci_idsel, pci_req_n[2], pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_inta_n tsu pci_clk rising 5 ? 5 ? 5 ? ns pci_gnt_n[0] tsu pci_clk rising 5 ? 5 ? 5 ? ns pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_rst_n, pci_devsel_n, pci_lock_n 3 thld pci_clk rising 0 ? 0 ? 0 ? ns per pci 2.2 pci_idsel, pci_req_n[2], pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_inta_n thld pci_clk rising 0 ? 0 ? 0 ? ns pci_eeprom_mdi tsu pci_clk rising, pci_eeprom_sk falling 15 ? 12 ? 10 ? ns table 6 ac timing characteristics - rc32334 (part 1 of 4)
16 of 30 august 31, 2004 idt 79rc32334?rev. y pci_eeprom_mdi thld pci_clk rising, pci_eeprom_sk falling 15 ? 12 ? 10 ? ns pci_eeprom_mdo, pci_eeprom_cs tdo pci_clk rising, pci_eeprom_sk falling ?15?12?10ns pci_eeprom_sk tdo pci_clk rising ? 15 ? 12 ? 10 ns pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n tdo pci_clk rising 262626ns per pci 2.2 pci_req_n[0], pci_gnt_[2], pci_gnt_n[1], pci_gnt_n[0], pci_inta_n tdo pci_clk rising 262626ns sdram controller sdram_245_dt_r_n tdo8 cpu_masterclk rising ? 15 ? 12 ? 10 ns chapter 11, figures 11.4 and 11.5 sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_s_n[1:0], sdram_bemask_n[3:0], sdram_cke tdo9 cpu_masterclk rising ? 12 ? 9 ? 8 ns sdram_addr_12 tdo10 cpu_masterclk rising ? 12 ? 9 ? 8 ns sdram_245_oe_n tdo11 cpu_masterclk rising ? 12 ? 9 ? 8 ns sdram_245_dt_r_n tdoh4 cpu_masterclk rising 1 ? 1 ? 1 ? ns sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_s_n[1:0], sdram_bemask_n[3:0] sdram_cke, sdram_addr_12, sdram_245_oe_n tdoh4 cpu_masterclk rising 2.5 ? 2.5 ? 2.5 ? ns dma dma_ready_n[1:0], dma_done_n[1:0] tsu7 cpu_masterclk rising 9 ? 7 ? 6 ? ns chapter 13, figure 13.4 dma_ready_n[1:0], dma_done_n[1:0] thld9 cpu_masterclk rising 1 ? 1 ? 1 ? ns interrupt handling cpu_int_n[5:4], cpu_int_n[2:0], cpu_nmi_n tsu9 cpu_masterclk rising 9 ? 9 ? 6 ? ns chapter 14, figure 14.12 cpu_int_n[5:4], cpu_int_n[2:0], cpu_nmi_n thld13 cpu_masterclk rising 1 ? 1 ? 1 ? ns pio pio[15:0] tsu7 cpu_masterclk rising 9 ? 7 ? 6 ? ns pio[15:0] thld9 cpu_masterclk rising 1 ? 1 ? 1 ? ns chapter 15, figures 15.9 and 15.10 pio[15:10], pio[8:0] tdo16 cpu_masterclk rising ? 15 ? 12 ? 10 ns pio[9] tdo19 cpu_masterclk rising ? 15 ? 12 ? 10 ns pio[15:10], pio[8:0] tdoh7 cpu_masterclk rising 1 ? 1 ? 1 ? ns pio[9] tdoh7 cpu_masterclk rising 1 ? 1 ? 1 ? ns timer timer_tc_n[0], timer_gate_n[0] tsu8 cpu_masterclk rising 9 ? 7 ? 6 ? ns timer_tc_n[0], timer_gate_n[0] thld10 cpu_masterclk rising 1 ? 1 ? 1 ? ns chapter 16, figures 16.6 and 16.7 timer_tc_n[0], timer_gate_n[0] tdo15 cpu_masterclk rising ? 15 ? 12 ? 10 ns timer_tc_n[0], timer_gate_n[0] tdoh6 cpu_masterclk rising 1 ? 1 ? 1 ? ns signal symbol reference edge rc32334 1 100mhz rc32334 1 133mhz rc32334 1 150mhz unit user manual timing diagram reference min max min max min max table 6 ac timing characteristics - rc32334 (part 2 of 4)
17 of 30 august 31, 2004 idt 79rc32334?rev. y uarts uart_rx[1:0], uart_tx[1:0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] tsu7 cpu_masterclk rising 15 ? 12 ? 10 ? ns chapter 17, figure 17.16 uart_rx[1:0], uart_tx[1:0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] thld9 cpu_masterclk rising 15 ? 12 ? 10 ? ns uart_rx[1:0], uart_tx[1:0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] tdo16 cpu_masterclk rising ? 15 ? 12 ? 10 ns uart_rx[1:0], uart_tx[1:0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] tdoh8 cpu_masterclk rising 1 ? 1 ? 1 ? ns spi interface spi_clk, spi_mosi, spi_miso tsu7 cpu_masterclk rising 15 ? 12 ? 10 ? ns chapter 18, figures 18.8 and 18.9 spi_clk, spi_mosi, spi_miso thld9 cpu_masterclk rising 15 ? 12 ? 10 ? ns spi_clk, spi_mosi, spi_miso tdo16 cpu_masterclk rising ? 15 ? 12 ? 10 ns spi_clk, spi_mosi, spi_miso tdoh8 cpu_masterclk rising 1 ? 1 ? 1 ? ns reset mem_addr[19:17] tsu10 cpu_coldreset_n rising 10 ? 10 ? 10 ? ms chapter 19 figures 19.8 and 19.9 mem_addr[19:17] thld10 cpu_coldreset_n rising 1 ? 1 ? 1 ? ns mem_addr[22:20], tsu22 cpu_masterclk rising 9 ? 7 ? 6 ? ns mem_addr[22:20] thld22 cpu_masterclk rising 1 ? 1 ? 1 ? ns debug interface debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n, ejtag_pcst[2:0] tsu20 cpu_coldreset_n rising 10 ? 10 ? 10 ? ms debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n, ejtag_pcst[2:0] thld20 cpu_coldreset_n rising 1 ? 1 ? 1 ? ns chapter 19, figure 19.9 and chapter 9, figure 9.2 debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n tdo20 cpu_masterclk rising ? 15 ? 12 ? 10 ns debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n tdoh20 cpu_masterclk rising 1 ? 1 ? 1 ? ns jtag interface jtag_tms, jtag_tdi, jtag_trst_n t 5 jtag_tck rising 10 ? 10 ? 10 ? ns see figure 4 below. jtag_tms, jtag_tdi, jtag_trst_n t 6 jtag_tck rising 10 ? 10 ? 10 ? ns jtag_tdo t 4 jtag_tck falling ? 10 ? 10 ? 10 ns signal symbol reference edge rc32334 1 100mhz rc32334 1 133mhz rc32334 1 150mhz unit user manual timing diagram reference min max min max min max table 6 ac timing characteristics - rc32334 (part 3 of 4)
18 of 30 august 31, 2004 idt 79rc32334?rev. y ejtag interface ejtag_tms, ejtag_debugboot t 5 jtag_tclk rising 4 ? 4 ? 4 ? ns see figure 4 below. ejtag_tms, ejtag_debugboot t 6 jtag_clk rising 2 ? 2 ? 2 ? ns jtag_tdo output delay time t tdodo, t 4 jtag_tck falling ? 6 ? 6 ? 6 ns jtag_tdi input setup time t tdis, t 5 jtag_tck rising 4 ? 4 ? 4 ? ns jtag_tdi input hold time t tdih, t 6 jtag_tck rising 2 ? 2 ? 2 ? ns jtag_trst_n low time t trstlow, t 12 ? 100 ? 100 ? 100 ? ns jtag_trst_n removal time t trstr, t 13 jtag_tck rising 3 ? 3 ? 3 ? ns ejtag_tpc output delay time t tpcdo, t 8 ejtag_dclk rising -1 3 -1 3 -1 3 ns ejtag_pcst output delay time t pcstdo, t 7 ejtag_dclk rising -1 3 -1 3 -1 3 ns 1. at all pipeline frequencies. 2. guaranteed by design. 3. pci_rst_n is tested per pci 2.2 as an asynchronous signal. signal symbol reference edge rc32334 1 100mhz rc32334 1 133mhz rc32334 1 150mhz unit user manual timing diagram reference min max min max min max table 6 ac timing characteristics - rc32334 (part 4 of 4)
19 of 30 august 31, 2004 idt 79rc32334?rev. y standard ejtag timing ? rc32334 figure 4 represents the timing diagram for the ejtag interface signals. the standard jtag connector is a 10-pin connector providing 5 signals and 5 ground pins. for standard ejtag, a 24-pin connector has been chosen providing 12 signals and 12 ground pins. this guarantees elim ination of noise problems by incorporating signal-ground ty pe arrangement. refer to the rc32334 user reference manual for connector pinout and mechanical specifications. figure 4 standard ejtag timing jtag_tdi/ejtag_dint_n ejtag_tms jtag_tdo/ejtag_tpc, ejtag_tpc[8:2] jtag_tdo jtag_tdo ejtag_tpc ejtag_pcst[2:0] jtag_trst_n jtag_tck ejtag_dclk ejtag_pcst t3 t14 t14 t1 t2 t15 t15 t9 t10 t5 t6 t4 t8 t7 t13 t12 t11 ejtag_tpc,ejtag_pcst[2:0] capture notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = t tck t4 = t tdodo t5 = t tdis t6 = t tdih t7 = t pcstdo t8 = t tpcdo t9 = t dckhigh t10 = t dcklow t11 = t dck t12 = t trstdo t13 = t trstr t14 = t tck rise, ttck fall t15 = t dck rise, t dck fall
20 of 30 august 31, 2004 idt 79rc32334?rev. y output loading for ac testing note: pci pins have been correlated to pci 2.2. recommended operation temperature and supply voltage dc electrical characteristics ? rc32334 commercial temperature range?rc32334 (ta = 0 c to +70 c commercial, ta = -40 c to +85 c industrial, v cc i/o = +3.3v 5%, v cc core = +3.3v 5%) signal cld all high drive signals 50 pf all low drive signals 25 pf figure 5 output loading for ac testing grade temperature gnd v cc io v cc core v cc p commercial 0 c to +70 c (ambient) 0v 3.3v5% 3.3v5% 3.3v5% industrial -40 c to +85 c (ambient) 0v 3.3v5% 3.3v5% 3.3v5% table 7 temperature and voltage parameter rc32334 1 pin numbers conditions minimum maximum input pads v il ? 0.8v b14, e13, f4, k1, l2, m1, m3, m4, m14, n1-n3, p14, r2, r16 ? v ih 2.0v ? ? low drive output pads v ol ? 0.4v a1, a12, a15, a16, b1, b2, b12, b15, c1-c3, c12, c13, c14, d12, d13, e1- e4, f1, f2, g1-g4, h1, h2, j1, j2, k2-k4, l1, l3, l4, p3, p14, r2, r15, r16, t16 |i out | = 6ma v oh v cc - 0.4v ? |i out | = 8ma v il ?0.8v ? v ih 2.0v ? ? high drive out- put pads v ol ? 0.4v a2-a4, a6-a11, a13, a14, b3, b4, b6-b11, b13, b16, c4, c6-c8, c10, c11, c15, c16, d1-d4, d6, d7, d10, d11, d14-d16, e14, e15, f3, f13-f16, g13-g16, h15, h16, j13, j14, k5, k13, k14, k16, l13-l16, m2, m13, m16, p2, p4, r1, r3, r4 |i out | = 7ma v oh v cc - 0.4v ? |i out | = 16ma v il ?0.8v ? v ih 2.0v ? ? pci drive input pads v il ? ? p1, r1, r10, t2, t3 per pci 2.2 v ih ?? table 8 dc electrical characteristics - rc32334 (part 1 of 2) ? + to device under test c ld v ref +1.5v
21 of 30 august 31, 2004 idt 79rc32334?rev. y capacitive load deration ? rc32334 refer to the idt document 79rc32334 ibis model located on the company?s web site. power consumption ? rc32334 note: this table is based on a 2:1 pi peline-to-bus clock ratio. power ramp-up there is no special requirement for how fast v cc i/o ramps up to 3.3v. however, all timing references are based on a stable v cc i/o. pci drive output pads v ol ? ? m15, n4-n7, n10-n16, p5-p13, p15, p16, r5-r9, r11-r14, t4- t15 per pci 2.2 v oh ?? v il ?? v ih ?? all pads c in ? 10pf all input pads except t3 and r3 ? c in 2 5pf 12pf t3 per pci 2.2 c in 3 ? 8pf r3 per pci 2.2 c out ? 10pf all output pads ? i/o leak ?10 a all non-internal pull-up pins input/output leakage i/o leak ?50 a all internal pull-up pins input/output leakage 1. at all pipeline frequencies. 2. applies only to pad t3. 3. applies only to pad r3. parameter 100mhz rc32334 133mhz rc32334 150mhz rc32334 unit conditions typical max. typical max. typical max. i cc normal mode 360 480 480 630 550 700 ma c l = (see figure 5, output loading for ac testing) t a = 25 o c v cc core = 3.46v (for max. values) v cc i/o = 3.46v (for max. values) v cc core = 3.3v (for typical values) v cc i/o = 3.3v (for typical values) standby mode 1 1. riscore 32300 cpu core enters standby mode by executing wait instructions. on-chip logic outside the cpu core continues to func tion. 250 370 330 480 390 540 ma power dissipation normal mode 1.2 1.7 1.5 2.2 1.7 2.4 w standby mode 1 .87 1.3 1.1 1.7 1.3 1.9 w table 9 power consumption parameter rc32334 1 pin numbers conditions minimum maximum table 8 dc electrical characteristics - rc32334 (part 2 of 2)
22 of 30 august 31, 2004 idt 79rc32334?rev. y power curves the following two graphs contain the simulated power curves that show power consumption at various bus frequencies. note: only pipeline frequencies that are integer multiples (2x, 3x, 4x) of bus frequencies are supported. figure 6 typical power usage - rc32334 . figure 7 maximum power usage - rc32334 100.0 200.0 300.0 400.0 500.0 600.0 15 20 25 30 35 40 45 50 55 60 65 70 75 system bus speed (mhz) icc (ma @3.3v i/o & core) 2x 3x 4x 100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 15 20 25 30 35 40 45 50 55 60 65 70 75 system bus speed (mhz) icc (ma @ 3.46v i/o & core) 2x 3x 4x
23 of 30 august 31, 2004 idt 79rc32334?rev. y absolute maximum ratings package pin-out ? 256-pbga pinout for rc32334 the following table lists the pin numbers and signal names for the rc32334. signal names ending with an ?_n? are active when lo w. symbol parameter min 1 1. functional and tested operating conditions are given in table 7. absolute maximum ratings are stress ratings only, and functional operation is not guaranteed beyond recommended operating voltages and temperatures. stresses beyond those listed may affect device reliability or cause permanent damage to the device. max 1 unit v cc supply voltage -0.3 4.0 v vi input voltage -0.3 5.5 v vimin input voltage - undershoot 2 2. all pci pads are fully compatible with pci specification version 2.2. -0.6 ? v tstg storage temperature -40 125 degrees c table 10 absolute maximum ratings pin function alt pin function alt pin function alt pin function alt a1 uart_cts_n[0] 1 e1 mem_cs_n[4] j1 debug_cpu_dma_n 1 n1 cpu_int_n[1] a2 sdram_245_oe_n e2 mem_cs_n[5] j2 debug_cpu_ack_n 1 n2 cpu_int_n[0] a3 sdram_cas_n e3 mem_cs_n[3] j3 v cc io n3 jtag_tdi a4 sdram_bemask_n[1] e4 mem_cs_n[2] j4 v ss n4 pci_ad[30] a5 sdram_ras_n e5 v cc io j5 v cc io n5 pci_ad[26] a6 mem_addr[3] 1 e6 v cc io j6 v ss n6 pci_ad[23] a7 mem_addr[7] 1 e7 v cc io j7 v ss n7 pci_ad[19] a8 mem_addr[11] 1 e8 v cc io j8 v ss n8 v cc core a9 sdram_cke e9 v cc io j9 v ss n9 v ss a10 sdram_bemask_n[2] e10 v cc io j10 v ss n10 pci_trdy_n a11 mem_addr[15] 1 e11 v cc io j11 v ss n11 pci_perr_n a12 mem_addr[19] 1 e12 v cc io j12 v cc io n12 pci_ad[15] a13 mem_data[10] e13 cpu_masterclk j13 mem_data[26] n13 pci_ad[1] a14 mem_data[20] e14 mem_data[15] j14 mem_data[5] n14 pci_ad[3] a15 mem_addr[23] e15 mem_data[16] j15 v cc core n15 pci_ad[4] a16 timer_tc_n[0] 2 e16 v cc core j16 v ss n16 pci_ad[2] b1 uart_rts_n[0] 1 f1 mem_cs_n[0] k1 ejtag_debugboot p1 pci_rst_n b2 uart_dsr_n[0] 1 f2 mem_cs_n[1] k2 ejtag_dclk p2 pci_gnt_n[2] 1 b3 sdram_we_n f3 mem_oe_n k3 debug_cpu_i_d_n 1 p3 dma_ready_n[1] 2 b4 sdram_bemask_n[0] f4 mem_wait_n 1 k4 debug_cpu_ads_n 1 p4 pci_req_n[0] b5 sdram_cs_n[1] f5 v cc io k5 v cc io p5 pci_ad[27] b6 mem_addr[2] 1 f6 v ss k6 v ss p6 pci_cbe_n[3] b7 mem_addr[6] 1 f7 v ss k7 v ss p7 pci_ad[20] b8 mem_addr[10] 1 f8 v ss k8 v ss p8 pci_ad[16] table 11 rc32334 256-pin pbga package pin-out (part 1 of 3)
24 of 30 august 31, 2004 idt 79rc32334?rev. y b9 sdram_addr_12 f9 v ss k9 v ss p9 pci_cbe_n[2] b10 sdram_bemask_n[3] f10 v ss k10 v ss p10 pci_devsel_n b11 mem_addr[16] 1 f11 v ss k11 v ss p11 pci_serr_n b12 mem_addr[20] 1 f12 v cc io k12 v cc io p12 pci_ad[14] b13 mem_data[11] f13 mem_data[1] k13 cpu_dt_r_n 2 p13 pci_ad[11] b14 cpu_coldreset_n f14 mem_data[30] k14 mem_data[6] p14 cpu_int_n[5] b15 mem_addr[25] f15 mem_data[31] k15 mem_data[24] p15 pci_ad[6] b16 mem_data[12] f16 mem_data[0] k16 mem_data[25] p16 pci_ad[5] c1 uart_rx[0] 1 g1 dma_ready_n[0] 2 l1 ejtag_pcst[0] r1 pci_req_n[2] 1 c2 uart_tx[0] 1 g2 mem_245_oe_n l2 jtag_trst_n r2 cpu_int_n[2] c3 uart_dtr_n[0] 1 g3 spi_mosi 2 l3 ejtag_pcst[1] 1 r3 pci_gnt_n[1] 2 c4 sdram_cs_n[0] g4 spi_miso 2 l4 ejtag_pcst[2] 1 r4 pci_gnt_n[0] c5 sdram_s_n[0] g5 v cc io l5 v cc io r5 pci_ad[29] c6 mem_addr[4] 1 g6 v ss l6 v ss r6 pci_ad[25] c7 mem_addr[9] 1 g7 v ss l7 v ss r7 pci_ad[22] c8 output_clk g8 v ss l8 v ss r8 pci_ad[18] c9 mem_addr[12] g9 v ss l9 v ss r9 pci_irdy_n c10 sdram_cs_n[3] g10 v ss l10 v ss r10 pci_lock_n c11 mem_addr[14] 1 g11 v ss l11 v ss r11 pci_cbe_n[1] c12 mem_addr[18] 1 g12 v cc io l12 v cc io r12 pci_ad[12] c13 mem_addr[22] 1 g13 mem_data[3] l13 mem_data[7] r13 pci_ad[10] c14 mem_addr[24] g14 mem_data[28] l14 mem_data[8] r14 pci_cbe_n[0] c15 mem_data[19] g15 mem_data[29] l15 mem_data[22] r15 uart_tx[1] 1 c16 mem_data[13] g16 mem_data[2] l16 mem_data[23] r16 cpu_int_n[4] d1 mem_we_n[1] h1 spi_ss_n 1 m1 jtag_tms t1 v ss d2 mem_we_n[3] h2 spi_sck 2 m2 jtag_tdo t2 pci_req_n[1] 1 d3 mem_we_n[2] h3 v cc io m3 ejtag_tms t3 pci_clk d4 mem_we_n[0] h4 v cc core m4 jtag_tck t4 pci_ad[31] d5 sdram_s_n[1] h5 v cc io m5 v cc io t5 pci_ad[28] d6 mem_addr[5] 1 h6 v ss m6 v cc io t6 pci_ad[24] d7 mem_addr[8] 1 h7 v ss m7 v cc io t7 pci_ad[21] d8 v ss h8 v ss m8 v cc io t8 pci_ad[17] d9 v cc core h9 v ss m9 v cc io t9 pci_frame_n d10 sdram_cs_n[2] h10 v ss m10 v cc io t10 pci_stop_n d11 mem_addr[13] 1 h11 v ss m11 v cc io t11 pci_par d12 mem_addr[17] 1 h12 v cc io m12 v cc io t12 pci_ad[13] d13 mem_addr[21] 1 h13 v ss p m13 mem_data[9] t13 pci_ad[9] pin function alt pin function alt pin function alt pin function alt table 11 rc32334 256-pin pbga package pin-out (part 2 of 3)
25 of 30 august 31, 2004 idt 79rc32334?rev. y d14 mem_data[17] h14 v cc p m14 cpu_nmi_n t14 pci_ad[8] d15 mem_data[14] h15 mem_data[27] m15 pci_ad[0] t15 pci_ad[7] d16 mem_data[18] h16 mem_data[4] m16 mem_data[21] t16 uart_rx[1] 1 pin function alt pin function alt pin function alt pin function alt table 11 rc32334 256-pin pbga package pin-out (part 3 of 3)
26 of 30 august 31, 2004 idt 79rc32334?rev. y pin layout figure 8 rc32334 chip ? top view 12345678910111213141516 vss vcc i/o the lighter shaded area shows the ground pins (vss) the darker shaded area shows the supply voltage pins (vcc i/o) a b c d e f g h j k l m n p r t vcc core vcc core vcc core vcc core vcc core vcc io vcc io vss vss vss vss vssp vccp vcc core vccp, vssp vss
27 of 30 august 31, 2004 idt 79rc32334?rev. y rc32334 alternate signal functions pin alt #1 alt #2 pin alt #1 alt #2 pin alt #1 alt #2 a1 pio[15] c3 pio[13] c3 h2 pio[9] pci_eeprom_sk a6 sdram_addr[3] c6 sdram_addr[4] j1 modebit[6] a7 sdram_addr[7] c7 sdram_addr[9] j2 modebit[4] a8 sdram_addr[11] c11 sdram_addr[14] k3 modebit[3] a11 sdram_addr[15] c12 modebit[8] k4 modebit[5] a12 modebit[9] c13 reset_boot_mode[1] k13 mem_245_dt_r_n sdram_245_dt_r_n a16 pio[2] timer_gate_n[0] d6 sdram_addr[5] l1 modebit[0] b1 pio[12] d7 sdram_addr[8] l3 modebit[1] b2 pio[14] d11 sdram_addr[13] l4 modebit[2] b6 sdram_addr[2] d12 modebit[7] p2 pci_inta_n (satellite) b7 sdram_addr[6] d13 reset_boot_mode[0] p3 pio[0] dma_done_n[1] b8 sdram_addr[10] f4 sdram_wait_n r1 pci_idsel (satellite) b11 sdram_addr[16] g1 pio[1] dma_done_n[0] r3 pci_eeprom_cs (satellite) pio[11] b12 reset_pci_host_mode g3 pio[10] pci_eeprom_mdo r15 pio[3] c1 pio[6] g4 pio[7] pci_eeprom_mdi t2 unused (satellite) c2 pio[5] h1 pio[8] t16 pio[4]
28 of 30 august 31, 2004 idt 79rc32334?rev. y rc32334 package drawing ? 256-pin pbga
29 of 30 august 31, 2004 idt 79rc32334?rev. y rc32334 package drawing ? page two
30 of 30 august 31, 2004 idt 79rc32334?rev. y corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: rischelp@idt.com phone: 408-284-8208 ordering information valid combinations 79rc32v334 - 100bb, 133bb, 150bb 79rc32v334 - 100bbg, 133bbg, 150bbg commercial commercial green 79rc32v334 - 100bbi, 133bbi, 150bbi 79rc32v334 - 100bbgi, 133bbgi, 150bbgi industrial industrial green 79rcxx v ddd sss pp operating voltage device type v = 3.3v 5% product type 79rc32 = 32-bit family product cpu frequency 100 mhz 133mhz package temp range/ process blank = commercial temperature (0 c to +70 c ambient) i = industrial temperature (-40 c to +85 c ambient) bb = 256-pin pbga 150mhz 334 bbg = 256-pin pbga (green package)

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